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Macros</h2></td></tr>
<tr class="memitem:ga7e6ace0b3fe51be13d0aeefaec243858"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga7e6ace0b3fe51be13d0aeefaec243858">XDPTX_VC_PAYLOAD_BUFFER_ADDR</a>&#160;&#160;&#160;0x0800</td></tr>
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<tr class="memitem:gaa7f8c59fb4ad94c697f8c1f0e2257730"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaa7f8c59fb4ad94c697f8c1f0e2257730">XDptx_GetDispIdTdtHTotal</a>(Tdt)</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: Link configuration field.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the DisplayPort TX core. </p>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: Core enables.</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: Core ID.</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: AUX channel interface.</div></td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: PHY configuration status.</div></td></tr>
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<tr class="memitem:ga1c299567502ff153b0e3ab3e04693a6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga1c299567502ff153b0e3ab3e04693a6b">XDPTX_GT_DRP_READ_DATA</a>&#160;&#160;&#160;0x02A4</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: DisplayPort audio.</div></td></tr>
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<tr class="memitem:gac37ba2f83438eeaf5330caba081b6394"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gac37ba2f83438eeaf5330caba081b6394">XDPTX_TX_AUDIO_CHANNELS</a>&#160;&#160;&#160;0x0304</td></tr>
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<tr class="memitem:ga3d4932d0e30b72d83325ed1f0eff1dc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga3d4932d0e30b72d83325ed1f0eff1dc0">XDPTX_TX_AUDIO_INFO_DATA</a>&#160;&#160;&#160;0x0308</td></tr>
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<tr class="memitem:gac7f55a04726ce5ab66d997aa3d398e5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gac7f55a04726ce5ab66d997aa3d398e5e">XDPTX_TX_AUDIO_EXT_DATA</a>&#160;&#160;&#160;0x0330</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.</div></td></tr>
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<tr class="memitem:gacbd281b359e81aeb0061598c1e6b702a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gacbd281b359e81aeb0061598c1e6b702a">XDPTX_STREAM2_MSA_START_OFFSET</a></td></tr>
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<tr class="memitem:gaae5d853532eb62707a2edd7ee4554b48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaae5d853532eb62707a2edd7ee4554b48">XDPTX_STREAM4_MSA_START</a>&#160;&#160;&#160;0x05A0</td></tr>
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<tr class="memitem:ga2b9f5cf2a4c0f2357e370ae7a81a647f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga2b9f5cf2a4c0f2357e370ae7a81a647f">XDPTX_STREAM4_MSA_START_OFFSET</a></td></tr>
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<tr><td colspan="2"><div class="groupHeader">DPTX core masks, shifts, and register values.</div></td></tr>
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<tr class="memitem:gae264ca15d40e43986c6cc994b200a272"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gae264ca15d40e43986c6cc994b200a272">XDPTX_INTERRUPT_MASK_HPD_IRQ_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:gae264ca15d40e43986c6cc994b200a272"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c0ab21d86f1f0ec70763c34e8f847e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga7c0ab21d86f1f0ec70763c34e8f847e6">XDPTX_INTERRUPT_MASK_HPD_EVENT_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="separator:ga7c0ab21d86f1f0ec70763c34e8f847e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba5f4a2d11d1c16eb7ac42e46a66a1dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaba5f4a2d11d1c16eb7ac42e46a66a1dd">XDPTX_INTERRUPT_MASK_REPLY_RECEIVED_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="separator:gaba5f4a2d11d1c16eb7ac42e46a66a1dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaff47f0199d49bf176dd0672a489feb21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaff47f0199d49bf176dd0672a489feb21">XDPTX_INTERRUPT_MASK_REPLY_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="separator:gaff47f0199d49bf176dd0672a489feb21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga125bfbf273206044e940840632432855"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga125bfbf273206044e940840632432855">XDPTX_INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="separator:ga125bfbf273206044e940840632432855"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6b65ca1c4851291a64cf787d493eee4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gad6b65ca1c4851291a64cf787d493eee4">XDPTX_INTERRUPT_MASK_EXT_PKT_TXD_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="separator:gad6b65ca1c4851291a64cf787d493eee4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5cdb033e7e35e695799d5e9891c5ae57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga5cdb033e7e35e695799d5e9891c5ae57">XDPTX_REPLY_STATUS_REPLY_RECEIVED_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:ga5cdb033e7e35e695799d5e9891c5ae57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1efa31f973089cf945b12dafdcac231f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga1efa31f973089cf945b12dafdcac231f">XDPTX_REPLY_STATUS_REPLY_IN_PROGRESS_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="separator:ga1efa31f973089cf945b12dafdcac231f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96428e20ecb1f0b2ea5627003e101237"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga96428e20ecb1f0b2ea5627003e101237">XDPTX_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="separator:ga96428e20ecb1f0b2ea5627003e101237"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab2578bc099e54c1739f06247a20c223d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gab2578bc099e54c1739f06247a20c223d">XDPTX_REPLY_STATUS_REPLY_ERROR_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="separator:gab2578bc099e54c1739f06247a20c223d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68aa2b53fec77188e095759d63fe4e4f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga68aa2b53fec77188e095759d63fe4e4f">XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_MASK</a>&#160;&#160;&#160;0x00000FF0</td></tr>
<tr class="separator:ga68aa2b53fec77188e095759d63fe4e4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa197dff781bf4b692800ff4c98ef3d47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaa197dff781bf4b692800ff4c98ef3d47">XDPTX_REPLY_STATUS_REPLY_STATUS_STATE_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="separator:gaa197dff781bf4b692800ff4c98ef3d47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab4be382ffcb05750de249a696fd7bc88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gab4be382ffcb05750de249a696fd7bc88">XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:gab4be382ffcb05750de249a696fd7bc88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7ff368b199653120745d35dbbb8b6a67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga7ff368b199653120745d35dbbb8b6a67">XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="separator:ga7ff368b199653120745d35dbbb8b6a67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5265dee8063dd9c922eb91264fc96359"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga5265dee8063dd9c922eb91264fc96359">XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ga5265dee8063dd9c922eb91264fc96359"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9d1375c1c5bef0030ee4803e4b5a3154"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga9d1375c1c5bef0030ee4803e4b5a3154">XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:ga9d1375c1c5bef0030ee4803e4b5a3154"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga53437c9a8d17203c20273fe49944ba21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga53437c9a8d17203c20273fe49944ba21">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="separator:ga53437c9a8d17203c20273fe49944ba21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e4e1a7bc814fd235d8b5bd4241cf993"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga8e4e1a7bc814fd235d8b5bd4241cf993">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ga8e4e1a7bc814fd235d8b5bd4241cf993"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf190b9960cbbd0b31bc8d94c3583e177"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaf190b9960cbbd0b31bc8d94c3583e177">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB</a>&#160;&#160;&#160;0x0</td></tr>
<tr class="separator:gaf190b9960cbbd0b31bc8d94c3583e177"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2656084077d48a700d0471ced29ec4f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga2656084077d48a700d0471ced29ec4f3">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:ga2656084077d48a700d0471ced29ec4f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2f8028fef49ced94003eff4317761b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaf2f8028fef49ced94003eff4317761b9">XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="separator:gaf2f8028fef49ced94003eff4317761b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5709d35da2320d69216ef309bd920447"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga5709d35da2320d69216ef309bd920447">XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="separator:ga5709d35da2320d69216ef309bd920447"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1a4cdc6a7c8e535bc11d9aa1f01f4081"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga1a4cdc6a7c8e535bc11d9aa1f01f4081">XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="separator:ga1a4cdc6a7c8e535bc11d9aa1f01f4081"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c8fb63a3f70f0237ff78744066a8821"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga5c8fb63a3f70f0237ff78744066a8821">XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="separator:ga5c8fb63a3f70f0237ff78744066a8821"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga383a99c5d27aa2a7f85880d0e8389d31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga383a99c5d27aa2a7f85880d0e8389d31">XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="separator:ga383a99c5d27aa2a7f85880d0e8389d31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b97cf8821d9d64b6373484c117649c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga8b97cf8821d9d64b6373484c117649c5">XDPTX_MAIN_STREAMX_MISC0_BDC_MASK</a>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="separator:ga8b97cf8821d9d64b6373484c117649c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab979cb6c78c5e4039c53ba8efe8a5583"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gab979cb6c78c5e4039c53ba8efe8a5583">XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="separator:gab979cb6c78c5e4039c53ba8efe8a5583"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:gab51366f59b9f87a2af70e177aaf46ec5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga91abe3ea71ac4c479e82039226669509"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga91abe3ea71ac4c479e82039226669509">XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="separator:ga91abe3ea71ac4c479e82039226669509"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga817aef846203cb2353121b0d6ae72aa4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga817aef846203cb2353121b0d6ae72aa4">XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC</a>&#160;&#160;&#160;0x2</td></tr>
<tr class="separator:ga817aef846203cb2353121b0d6ae72aa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8f14cc46979dd9cd1805194fc864e51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gab8f14cc46979dd9cd1805194fc864e51">XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="separator:gab8f14cc46979dd9cd1805194fc864e51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafbde22ffe7105d66d1ad969a7bda05b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gafbde22ffe7105d66d1ad969a7bda05b0">XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="separator:gafbde22ffe7105d66d1ad969a7bda05b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab56aa216312e71f1ec74fc5ada78df29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gab56aa216312e71f1ec74fc5ada78df29">XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="separator:gab56aa216312e71f1ec74fc5ada78df29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12d409bfe12707708286f1b2d9b9550c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga12d409bfe12707708286f1b2d9b9550c">XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="separator:ga12d409bfe12707708286f1b2d9b9550c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga870bcaceda2377ffca92a46d251670ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga870bcaceda2377ffca92a46d251670ea">XDPTX_MAIN_STREAMX_MISC1_STEREO_VID_ATTR_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="separator:ga870bcaceda2377ffca92a46d251670ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga42d9dd623a58b4c7345c8c8bb23324ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga42d9dd623a58b4c7345c8c8bb23324ae">XDPTX_PHY_CONFIG_PHY_RESET_ENABLE_MASK</a>&#160;&#160;&#160;0x0000000</td></tr>
<tr class="separator:ga42d9dd623a58b4c7345c8c8bb23324ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaae0c20e361280cace984f7fff18271b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gaae0c20e361280cace984f7fff18271b6">XDPTX_PHY_CONFIG_PHY_RESET_MASK</a>&#160;&#160;&#160;0x0000001</td></tr>
<tr class="separator:gaae0c20e361280cace984f7fff18271b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafa7579fc809a60ec3496f2c75e462525"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gafa7579fc809a60ec3496f2c75e462525">XDPTX_PHY_CONFIG_GTTX_RESET_MASK</a>&#160;&#160;&#160;0x0000002</td></tr>
<tr class="separator:gafa7579fc809a60ec3496f2c75e462525"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae6c85c6919805d15697f133b970f6a0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gae6c85c6919805d15697f133b970f6a0e">XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK</a>&#160;&#160;&#160;0x0000100</td></tr>
<tr class="separator:gae6c85c6919805d15697f133b970f6a0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="separator:gab35e97c559c06d99ec74a66d3e7dfe2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga024c99d0a0ffcb86dd4fe5c4e88ea540"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga024c99d0a0ffcb86dd4fe5c4e88ea540">XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK</a>&#160;&#160;&#160;0x0000800</td></tr>
<tr class="separator:ga024c99d0a0ffcb86dd4fe5c4e88ea540"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="memitem:ga93d0e79c17341380bc09c89b316be10d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga93d0e79c17341380bc09c89b316be10d">XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_MASK</a>&#160;&#160;&#160;0x000E000</td></tr>
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<tr class="memitem:ga523ae9b3ebb05991b434693ae285bdd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga523ae9b3ebb05991b434693ae285bdd0">XDPTX_PHY_CONFIG_TX_PHY_LOOPBACK_SHIFT</a>&#160;&#160;&#160;13</td></tr>
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<tr class="memitem:gae60d69bceb3c528d9c64ed41a3500f16"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#gae60d69bceb3c528d9c64ed41a3500f16">XDPTX_PHY_STATUS_LANES_0_1_READY_MASK</a>&#160;&#160;&#160;0x00000013</td></tr>
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<tr class="memitem:ga7af4dd4c3cef9ccfe2b2639aafb18dc3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga7af4dd4c3cef9ccfe2b2639aafb18dc3">XDPTX_PHY_STATUS_ALL_LANES_READY_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
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<tr class="memitem:ga7d9d092698674c66fc88d4b2edec5da8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga7d9d092698674c66fc88d4b2edec5da8">XDPTX_GT_DRP_COMMAND_DRP_ADDR_MASK</a>&#160;&#160;&#160;0x000F</td></tr>
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<tr class="memitem:ga8f0ec89901485a76219b83547ee1e032"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dptx__v3__0.html#ga8f0ec89901485a76219b83547ee1e032">XDPTX_GT_DRP_COMMAND_DRP_RW_CMD_MASK</a>&#160;&#160;&#160;0x0080</td></tr>
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<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Receiver capability field.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the DisplayPort Configuration Data (DPCD) of the downstream device. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link configuration field.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link/sink status field.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Automated testing sub-field.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Sink control field.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Sideband message buffers.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Event status indicator field.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Field addresses and sizes.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Receiver capability field masks,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>shifts, and register values. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link configuration field masks,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>shifts, and register values. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DisplayPort Configuration Data: Link/sink status field masks, shifts,</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>and register values. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Field addresses and sizes.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Address mapping for the Extended Display Identification Data (EDID) of the downstream device. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Register offsets for the</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Tiled Display Topology (TDT) section data block. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Extended Display Identification Data: Masks, shifts, and register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>values for the Tiled Display Topology (TDT) section data block. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Stream identification.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Multi-stream transport (MST) definitions. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Sideband message codes when the driver is in MST mode.</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definitions.</div></td></tr>
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